View ADP3806JRUZ-125RL_3764417.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

high frequency switch mode li-ion battery charger adp3806 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features li-ion battery charger three battery voltage options selectable 12.525 v/16.700 v selectable 12.600 v/16.800 v adjustable high end-of-charge voltage accuracy 0.4% @ 25c 0.6% @ 5c to 55c 0.7% @ 0c to 85c programmable charge current with rail-to-rail sensing system current sense with reverse input protection soft start charge current undervoltage lockout bootstrapped synchronous drive for external nmos programmable oscillator frequency oscillator sync pin low current flag trickle charge applications portable computers fast chargers general description the adp3806 is a complete li-ion battery-charging ic. the device combines high output voltage accuracy with constant current control to simplify the implementation of constant- current, constant-voltage (cccv) chargers. the adp3806 is available in three options. the adp3806-12.6 guarantees the final battery voltage selected is 12.6 v or 16.8 v 0.6%. the adp3806-12.5 guarantees 12.525 v/16.7 v 0.6%, and the adp3806 is adjustable using two external resistors to set the battery voltage. the current sense amplifier has rail-to-rail inputs to operate accurately under low dropout and short-circuit conditions. the charge current is programmable with a dc voltage on iset. a second differential amplifier senses the system current across an external sense resistor and outputs a linear voltage on the isys pin. the bootstrapped synchronous driver allows the use of two nmos transistors for lower system cost. functional block diagram ? + select 12.6v/16.8v bootstrapped synchronous driver cs+ oscillator cs? comp ref agnd bat sd ct sw reg pgnd vc cbst drvh drvl sys+ sys ? isys iset lc sync limi t v ref 2.5v v ref adp3806 bstreg batsel vth drvlsd ? + ? + + ? amp1 amp2 13 8 9 7 6 11 15 12 10 21 1 22 23 24 20 19 18 17 3 2 4 drvlsd sd in 5 16 14 ? + ? + v ref + v reg uvlo bias logic control 02611-001 g m 1 g m 2 ? figure 1.
adp3806 rev. c | page 2 of 16 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 10 charge current control ............................................................ 10 final battery voltage control ................................................... 11 oscillator and pwm .................................................................. 11 7 v bootstrap regulator ............................................................ 12 bootstrapped synchronous driver .......................................... 12 2.5 v precision reference.......................................................... 12 6 v regulator .............................................................................. 12 lc ................................................................................................. 12 system current sense ................................................................ 12 shutdown..................................................................................... 13 uvlo........................................................................................... 13 start-up sequence....................................................................... 13 loop feed forward .................................................................... 13 application information................................................................ 14 design procedure ....................................................................... 14 battery voltage settings............................................................. 14 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 11/06rev. b to rev. c updated format..................................................................universal changes to table 1............................................................................ 3 changes to table 3............................................................................ 6 updated outline dimensions ....................................................... 16 changes to ordering guide .......................................................... 16 2/04rev. a to rev. b changes to specifications.................................................................2 changes to ordering guide .............................................................4 updated outline dimensions....................................................... 14 6/03rev. 0 to rev. a updated specifications .....................................................................2 updated absolute maximum ratings ............................................4 changes to ordering guide .............................................................4 updated outline dimensions....................................................... 14 2002revision 0: initial version
adp3806 rev. c | page 3 of 16 specifications @ 0c t a 100c, v cc = 16 v, unless otherwise noted. table 1. parameter 1 symbol conditions min typ max unit battery sense input adp3806-12.6 v and 16.8 v v bat t a = 25c, 13 v v cc 20 v ?0.4 +0.4 % adp3806-12.525 v and 16.7 v v bat 5c t a 55c ?0.6 +0.6 % v bat 0c t a 85c ?0.7 +0.7 % input resistance r bat part in operation 250 350 k input current i bat(sd) part in shutdown 0.2 1.0 a battery sense input v bat = 2.5 v v bat t a = 25c, 13 v v cc 20 v ?0.5 +0.5 % v bat 0c t a 85c ?0.7 +0.7 % input current operating batsel = open, part in operation 0.2 1.0 a input current shutdown batsel = 100 k to gnd, part in shutdown 0.2 1.0 a oscillator maximum frequency 2 f ct 1000 khz frequency variation 3 f ct ct = 180 pf 210 250 290 khz ct charge current i ct 125 150 175 a 0% duty cycle threshold @ comp pin 1.0 v maximum duty cycle threshold @ comp pin 2.5 v sync input high sync h 2.2 v sync input low sync l 0.8 v sync input current i sync 0.2 1.0 a gate drive on resistance r on i l = 10 ma 6 10 rise, fall time tr, t f c l = 1 nf, drvl and drvh 35 ns overlap protection delay t op drvl falling to drvh rising, 50 ns drvh falling to drvl rising sw bias current part in shutdown, v sw = 12.6 v 0.2 1.0 a bst cap refresh threshold v bst ? v sw 3.7 v current sense amplifier input common-mode range v cs(cm) v cs+ and v cs? 0.0 v cc + 0.3 v input differential mode range v cs(dm) v cs 4 0.0 160 mv input offset voltage 5 v cs(vos) 0 v v cs(cm) v cc 1.0 mv gain 5 25 v/v input bias current v cs(ib) 0 v v cs(cm) v cc , part in operation 50 100 a input offset current v cs(ios) 0 v v cs(cm) v cc 1.0 2.0 a input bias current part in shutdown 0.2 1.0 a drvl shutdown threshold v cs(sd) measured between v cs+ and v csC 48 mv system current sense 6 input common-mode range v sys(cm) sys+ and sys?, i l = 0 ma, v isys = 3 v 4.0 v cc + 0.3 v input differential range v sys(dm) (v sys+ ) ? (v sysC ) 0 100 mv input offset voltage 0.5 mv input bias current, sys+ i b(sys+) v sys(dm) = 0 v, v sys(cm) = 16 v 200 300 a input bias current, sysC i b(sys?) v sys(dm) = 0 v, v sys(cm) = 16 v 70 125 a voltage gain 10 v v sys(cm) v cc + 0.3 v, i l = 100 a 48.5 50 51.5 v/v i sys output range v isys i l = 1 ma 7 , v sys(cm) > 6 v 0 5.0 v limit output threshold v th(limit) v limit 0.2 v, 50 k pull up to 5 v 2.3 2.5 2.7 v limit output voltage v o(limit) v isys > 2.65 v, i sink = 700 a 0.1 0.2 v
adp3806 rev. c | page 4 of 16 parameter 1 symbol conditions min typ max unit iset input charge current programming function v iset/vcs 0.0 v < v iset 4.0 v 25 v/v programming function accuracy v iset = 4.0 v, 1 v v cs(cm) 16 v ?5 1.0 +5 % v iset = 0.50 v, 1 v v cs(cm) 10 v ?30 10 +30 % 5c t a 55c, v iset = 206 mv, v cs(cm) = 5 v and 10 v ?46.7 +33 % iset bias current i b 0.0 v v iset 4.0 v 0.2 1.0 a batsel input v bat = 12.6 v 2.0 v v bat = 16.8 v 0.8 v batsel input current 0.2 5.0 a boost regulator output output voltage v bstreg c l = 0.1 f 6.8 7.0 7.2 v output current 8 i bstreg 3.0 5.0 ma analog regulator output output voltage v reg c l = 10 nf 5.8 6.0 6.2 v output current 8 i reg 3.0 5.0 ma precision reference output output voltage v ref 2.47 2.5 2.53 v output current 8 i ref 0.5 1.1 ma shutdown (sd) on sd h 2.0 v off sd l 0.8 v sd input current 0.2 1.0 a power supply on supply current i syon no external loads, uvlo v cc 20 v 6.0 8.0 ma off supply current i syoff no external loads, v cc 20 v 1.0 5.0 a uvlo threshold voltage v uvlo turn on 5.65 6.0 6.25 v uvlo hysteresis turn off 0.1 0.3 0.5 v lc output output voltage low high current mode 9 , i sink = 100 a 0.1 0.4 v output voltage high low current mode 10 external v output reverse leakage protection leakage current i disch v cc = floating, v bat = 12.6 v 1 5 a overcurrent comparator overcurrent threshold v cs(oc) 180 mv response time t oc v cs > 180 mv to comp < 1 v 2 s overvoltage comparator overvoltage threshold v bat(ov) 120 % response time t ov v bat > 120% to comp < 1 v 2 s 1 all limits at temperature extremes are gua ranteed via correlation using standard st atistical quality control (sqc) methods. 2 guaranteed by design, not tested in production. 3 if sync function is used, then f sync must be greater than f ct but less than 120% of f ct . 4 v cs = (v cs+ ) ? (v cs? ). 5 accuracy guaranteed by iset input, programming func tion accuracy specification. 6 system current sense is active during shutdown. 7 load current is supplied through sys+ pin. 8 guaranteed output current from 0 to minimu m specified value to maintain regulation. 9 v bat < 93% of final or v cs > 25 mv. 10 v bat 93% of final or v cs 25 mv.
adp3806 rev. c | page 5 of 16 absolute maximum ratings table 2. parameter ratings input voltage (v cc ) ?0.3 v to +25 v bat, cs+, cs? ?0.3 v to v cc + 0.3 v sys+, sys? ?25 v to +25 v bst ?0.3 v to +30 v bst to sw ?0.3 v to +8 v sw to pgnd ?4 v to +25 v drvl to pgnd ?0.3 v to +8 v iset, batsel, sd , sync, ct, limit, isys, lc ?0.3 v to +10 v comp ?0.3 v to +3 v gnd to pgnd ?0.3 v to +0.3 v operating ambient temperature range 0c to 100c ja 115c/w operating junction temperature range 0c to 125c storage temperature range ?65c to +150c lead temperature (soldering 10 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adp3806 rev. c | page 6 of 16 pin configuration and fu nction descriptions top view (not to scale) 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 adp3806 lc comp sd ref reg vcc sys? sys+ isys sync ct limit agnd bat batsel iset cs? sw drvh bst bstreg cs+ pgnd drvl 02611-002 figure 2. pin configuration table 3. pin function descriptions pin no. mnemonic function 1 vcc supply voltage. 2 sys? negative system current sense input. 3 sys+ positive system current sense input. 4 isys system current sense output. 5 limit system current sense limit output. 6 ct oscillator timing capacitor. 7 sync oscillator synchronization pin. 8 reg 6.0 v analog regulator output. 9 ref 2.5 v precision reference output. 10 sd shutdown control input. 11 comp external compensation node. 12 lc low current output. 13 agnd analog ground. 14 bat battery sense input. 2.5 v for adp3806. 12.525 v or 16.7 v for adp3806-12.5. 12.6 v or 16.8 v for adp3806-12.6. 15 batsel battery voltage sense input. high = three cells, low = four cells. 16 iset charge current program input. 17 cs? negative current sense input. 18 cs+ positive current sense input. 19 pgnd power ground. 20 drvl low drive output. this switches between reg and pgnd. 21 bstreg 7.0 v regulator output for boost. 22 bst floating bootstrap supply for drvh. 23 drvh high drive output. this switches between sw and bst. 24 sw buck switching node reference for drvh.
adp3806 rev. c | page 7 of 16 typical performance characteristics 30 25 20 15 10 5 0 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 number of parts v bat accuracy (%) 02611-003 v cc = 16v t a = 25c figure 3. v bat accuracy distribution ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 v cc = 16v 0 20406080 v bat accuracy (%) 02611-004 temperature (c) 100 figure 4. v bat accuracy vs. temperature ?0.10 ?0.05 0.05 0.10 0 t a = 25c 10 12 14 16 18 20 v bat accuracy (%) 02611-005 v cc (v) figure 5. v bat accuracy vs. v cc v cc = 16v ?0.5 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 0 20406080 v ref accuracy (%) 02611-006 temperature (c) 100 figure 6. v ref accuracy vs. temperature 02611-007 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0.02 0.04 0.06 0.08 0.10 0 51 01 5 v ref accuracy (%) v cc (v) 2 0 t a = 25c figure 7. v ref accuracy vs. v cc 4.0 4.4 4.8 5.2 5.6 6.0 no loads 10 12 14 16 18 20 on supply current (ma) v cc (v) t a = 25c t a = 100c 02611-008 t a = 0c figure 8. on supply current vs. v cc
adp3806 rev. c | page 8 of 16 0 2 4 6 8 10 12 14 16 18 0 500 1000 1500 2000 2500 3000 3500 supply current (ma) driver load capacitance (pf) v cc = 16v t a = 25c f osc = 250khz 02611-009 figure 9. supply current vs. driver load capacitance 1.0 0.8 0.6 0.4 0.2 0 10.0 12.5 15.0 17.5 20.0 off suppply current (a) v cc (v) t a = 25c t a = 100c t a = 0c 02611-010 figure 10. off supply current vs. v cc 0 100 200 300 400 500 600 0 200 400 600 800 frequency (khz) ct (pf) 02611-011 v cc = 16v t a = 25c figure 11. oscillato r frequency vs. ct 0 1 2 3 4 5 6 50k ? to 5v 2.0 3.2 3.0 2.8 2.6 2.4 2.2 v limit (v) v isys (v) 50k ? to 2.5v 02611-012 v cc = 16v t a = 25c figure 12. v limit vs. v isys driver sourcing driver sinking v cc = 16v 10 8 6 4 2 0 0 20406080 driver on resistance ( ? ) temperature (c) 02611-013 100 figure 13. driver on resistance vs. temperature drvl 5v/div 200ns/div drvh 5v/div 0 2611-014 v cc = 16v t a = 25c figure 14. driver waveforms
adp3806 rev. c | page 9 of 16 80 82 84 86 88 90 92 94 96 98 100 0.1 1 10 conversion efficiency (%) charge current (a) 02611-015 v cc = 19v v bat = 12.4v t a = 25c figure 15. conversion efficiency vs. charge current 82 84 86 88 90 92 94 96 345678910111213 conversion efficiency (%) v bat (v) v cc = 19v t a = 25c i charge = 3a 02611-016 i charge = 2a figure 16. conversion efficiency vs. battery voltage 100 95 90 85 80 75 70 2 4 6 8 10 12 14 conversion efficiency (%) v bat (v) 19v in 85c 19v in 0c 02611-017 figure 17. conversion efficiency vs. battery voltage at given temperatures
adp3806 rev. c | page 10 of 16 theory of operation the adp3806 combines a bootstrapped synchronous switching driver with programmable current control and accurate final battery voltage control in a constant-current, constant-voltage (cccv) li-ion battery charger. high accuracy voltage control is needed to safely charge li-ion batteries, which are typically specified at 4.2 v 1% per cell. for a typical notebook computer battery pack, three or four cells are in series, giving a total voltage of 12.6 v or 16.8 v. the adp3806 is available in three versions, a selectable 12.525 v or 16.7 v output, a selectable 12.6 v or 16.8 v output, and an adjustable output. the adjustable output can be programmed for a wide range of battery voltages using two external precision resistors. another requirement for safely charging li-ion batteries is accurate control of the charge current. the actual charge current depends on the number of cells in parallel within the battery pack. typically, this is in the range of 2 a to 3 a. the adp3806 provides flexibility in programming the charge current over a wide range. an external resistor is used to sense the charge current and this voltage is compared to a dc input voltage. this programmability allows the current to be changed during charging. for example, the charge current can be reduced for trickle charging. the synchronous driver provides high efficiency when charging at high currents. efficiency is important mainly to reduce the amount of heat generated in the charger but also to stay within the power limits of the ac adapter. with the addition of a boot- strapped high side driver, the adp3806 drives two external power nmos transistors for a simple, lower cost power stage. the adp3806 also provides an uncommitted current sense amplifier. this amplifier provides an analog output pin for monitoring the current through an external sense resistor. the amplifier can be used anywhere in the system that high side current sensing is needed. charge current control amp1 in figure 18 has a differential input to amplify the voltage drop across an external sense resistor r cs . the input common-mode range is from ground to v cc , allowing current control in short-circuit and low dropout conditions. the gain of amp1 is internally set to 25 v/v for low voltage drop across the sense resistor. during constant current (cc) mode, g m 1 forces the voltage at the output of amp1 to be equal to the external voltage at the iset pin. by choosing r cs and v iset appropriately, a wide range of charge currents can be programmed. cs ref charge r v i = 25 (1) select 12.6v16.8v bootstrapped sycroous driver v i cs oscillator l1 v ref v reg uvlo bias cs r3 249 comp ref 2.5v agd bat sd ct sw reg 6.0v pgd v cc bst battery 12.6v16.8v 7.0v c10 0.1f drv sys sys isys iset logic cotrol lc syc limit v ref 2.5v system dcdc v ref adp3806 12 1 fd56990a c15 22f c14 2.2f r7 2 100k otes 1 adp3806-12.6 adp3806-12.5 r11 sort r12 ope adp3806 r11 412k r12 102k r14 ope. 2 r7 ope if lc fuctio is ot used. c17 100nf c7 200pf c6 180pf r8 56 c8 0.22f r11 1 412k 0.1 r1 2.2 c13 22nf c16 22f c9 100nf 12 1 fd56990a 22 r cs 40m r4 249 r5 6.81k r6 7.5k r13 10 c2 470nf c1 470nf bstreg batsel drvlsd i sd v t drvlsd r2 2.2 amp2 r ss 10m amp1 drvl r12 1 412k 0.1 r14 1 0 02611-018 g m 1 g m 2 figure 18. typical application
adp3806 rev. c | page 11 of 16 typical values of r cs range from 25 m to 50 m, and the input range of iset is from 0 v to 4 v. if, for example, a 3 a charger is required, r cs could be set to 40 m and v iset = 3 v. the power dissipation in r cs should be kept below 500 mw. in this example, the power is a maximum of 360 mw. once r cs has been chosen, the charge current can be adjusted during operation with v iset . lowering v iset to 125 mv gives a charge current of 125 ma for trickle charging. the r3, r4, and c13 component s provide high frequency filtering for the current sense signal. final battery voltage control as the battery approaches its final voltage, the adp3806 switches from cc mode to constant voltage (cv) mode. the change is achieved by the common output node of g m 1 and g m 2. only one of the two outputs controls the voltage at the comp pin. both amplifiers can only pull down on comp, such that when either amplifier has a positive differential input voltage, its output is not active. for example, when the battery voltage, v bat , is low, g m 2 does not control comp. when the battery voltage reaches the desired final voltage, g m 2 takes control of the loop, and the charge current is reduced. amplifier g m 2 compares the battery voltage to the internal reference voltage of 2.5 v. in the case of the adp3806-12.5 and adp3806-12.6, an internal resistor divider sets the selectable final battery voltage. when batsel is high, the final battery voltage is set to three cells (12.6 v or 12.525 v). batsel can be tied to reg for this state. when batsel is tied to ground, v bat equals four cells (16.8 v or 16.7 v). batsel has a 2 a pull-up current as a fail- safe to select three cells when it is left open. the reference and internal resistor divider are referenced to the agnd pin, which should be connected close to the negative terminal of the battery to minimize sensing errors. in contrast, the adp3806 requires external, precision resistors. the divider ratio should be set to divide the desired final voltage down to 2.5 v at the bat pin 1 5.2 ? = v v r12 r11 battery (2) these resistors should have a parallel impedance of approximately 80 k to minimize bias current errors. when the adp3806 is in shutdown, an internal switch disconnects the bat pin as shown in figure 19. this disconnects the resistor (r11) from the battery and minimizes leakage. the resistance of the internal switch is less than 200 . v ref sd battery rr11 412k ? 0.1% adp3806 r12 102k? 0.1% bat batsel g m 2 + 02611-019 figure 19. battery sense disconnect circuit oscillator and pwm the oscillator generates a triangle waveform between 1 v and 2.5 v. this is compared to the voltage at the comp pin, setting the duty cycle of the driver stage. when v comp is below 1 v, the duty cycle is zero. above 2.5 v, the duty cycle reaches its maximum. min off time bstreg bst drvh sw in drvl cbst pgnd 1v 1v q1 q2 delay drvlsd sd delay cmp3 cmp2 cmp1 + ? + ? adp3806 bootstrapped synchronous driver 02611-020 figure 20. bootstrapped synchronous driver
adp3806 rev. c | page 12 of 16 the oscillator frequency is set by the external capacitor at the ct pin and the internal current source of 150 a according to the following formula: v5.1cr2.2 a150 f osc = (3) a 180 pf capacitor sets the frequency to 250 khz. the frequency can also be synchronized to an external oscillator by applying a square wave input on sync. the sync function is designed to allow increases only in the oscillator frequency. the f sync should be no more than 20% higher than f osc . the duty cycle of the sync input is not important and can be anywhere between 5% and 95%. 7 v bootstrap regulator the driver stage is powered by the internal 7 v bootstrap regulator available at the bstreg pin. because the switching currents are supplied by this regulator, decoupling must be added. a 0.1 f capacitor should be placed close to the adp3806, with the ground side connected close to the power ground pin (pgnd). this supply is not recommended for use externally due to high switching noise. bootstrapped synchronous driver the pwm comparator controls the state of the synchronous driver shown in figure 20. a high output from the pwm comparator forces drvh on and drvl off. the drivers have an on resistance of approximately 6 for fast rise and fall times when driving external mosfets. furthermore, the bootstrapped drive allows an external nmos transistor for the main switch instead of a pmos. an external boost diode should be connected between bstreg and bst, and a boost capacitor of 0.1 f must be added externally between bst and sw. the voltage between bst and sw is typically 6.5 v. the drvl pin switches between bstreg and pgnd. the 7 v output of bstreg drives the external nmos with high vgs to lower the on resistance. pgnd should be connected close to the source pin of the external synchronous nmos. when drvl is high, this turns on the lower nmos and pulls the sw node to ground. at this point, the boost capacitor is charged up through the boost diode. when the pwm switches high, drvl is turned off and drvh turns on. drvh switches between bst and sw. when drvh is on, the sw pin is pulled up to the input supply (typically 16 v), and bst rises above this voltage by approximately 6.5 v. overlap protection is included in the driver to ensure that both external mosfets are not on at the same time. when drvh turns off the upper mosfet, the sw node goes low due to the inductor current. the adp3806 monitors the sw voltage, and drvl goes high to turn on the lower mosfet when sw goes below 1 v. when drvl turns off, an internal timer adds a delay of 50 ns before turning on drvh. when the charge current is low, the drvlsd comparator signals the driver to turn off the low side mosfet and drvl is held low. as shown in figure 20, the drvlsd comparator looks at the output of amp1. the drvlsd threshold is set to 1.2 v, corresponding to 48 mv differential voltage between the cs pins. the driver stage monitors the voltage across the bst capacitor with cmp3. when this voltage is less than 4 v, cmp3 forces a minimum offtime of 200 ns. this ensures that the bst capacitor is charged even during drvlsd. however, because a minimum off time is only forced when needed, the maximum duty cycle is greater than 99%. 2.5 v precision reference the voltage at the bat pin is compared to an internal precision, low temperature drift reference of 2.5 v. the reference is available externally at the ref pin. this pin should be bypassed with a 100 pf capacitor to the analog ground pin (agnd). the reference can be used as a precision voltage externally. however, the current draw should not be greater than 100 a, and noisy, switching type loads should not be connected. 6 v regulator the 6 v regulator supplies power to most of the analog circuitry on the adp3806. this regulator should be bypassed to agnd with a 0.1 f capacitor. this reference has a 3 ma source capability to power external loads if needed. lc the adp3806 provides a low current (lc) logic output to signal when the current sense voltage (v cs ) is below a fixed threshold and the battery voltage is greater than 95%. lc is an open-drain output that is pulled low when v cs is above the threshold. when the low current threshold condition is reached, lc is pulled high by an external resistor to ref or another appropriate pull-up voltage. to determine when lc goes low, an internal comparator senses when the current falls below 12.5% of full scale (20 mv across the cs pins). the comparator has hysteresis to prevent oscillation around the trip point. to prevent false triggering (such as during soft start), the comparator is only enabled when the battery voltage is within 5% of its final voltage. as the battery charges up, the comparator does not go low even if the current falls below 12.5% as long as the battery voltage is below 95% of full scale. once the battery has risen above 95%, the comparator is enabled. this pin can be used to indicate the end of the charge process. system current sense an uncommitted differential amplifier is provided for additional high side current sensing. this amplifier, amp2, has a fixed gain of 50 v/v from the sys+ and sys? pins to the analog output at isys. isys has a 1 ma source capability to
adp3806 rev. c | page 13 of 16 drive an external load. the common-mode range of the input pins is from 4 v to v cc . this amplifier is the only part of the adp3806 that remains active during shutdown. the power to this block is derived from the bias current on the sys+ and sys? pins. a separate comparator at the limit pin signals when the voltage on the isys pin exceeds 2.5 v typically. the internal comparator has an open-drain output that produces the function shown in the figure 12 graph of v limit vs. v isys . the limit pin should be externally pulled up to 5 v, 2.5 v, or some other voltage as needed through a resistor. this graph was taken with a 50 k pull-up resistor to 5 v and to 2.5 v. when isys is below 2.4 v, the limit pin has high output impedance. the open-drain output is capable of sinking 700 a when the threshold is exceeded. this comparator is turned off during shutdown to conserve power. shutdown a high impedance cmos logic input is provided to turn off the adp3806. when the voltage on sd is less than 0.8 v, the adp3806 is placed in low power shutdown. with the exception of the system current sense amplifier, amp2, all other circuitry is turned off. the reference and regulators are pulled to ground during shutdown and all switching is stopped. during this state, the supply current is less than 5 a. in addition, the bat, cs+, cs?, and sw pins go to high impedance to minimize current drain from the battery. uvlo undervoltage lock-out, uvlo, is included in the adp3806 to ensure proper startup. as v cc rises above 1 v, the reference and regulators track v cc until they reach their final voltages. however, the rest of the circuitry is held off by the uvlo comparator. the uvlo comparator monitors both regulators to ensure they are above 5 v before turning on the main charger circuitry. this occurs when v cc reaches 6 v. monitoring the regulator outputs ensures that the charger circuitry and driver stage have sufficient voltage to operate normally. the uvlo comparator includes 300 mv of hysteresis to prevent oscillations near the threshold. start-up sequence during a startup from either sd going high or v cc exceeding the uvlo threshold, the adp3806 initiates a soft start sequence. the soft start timing is set by the compensation capacitor at the comp pin and an internal 40 a source. initially, both drvh and drvl are held low until comp reaches 1 v. this delay time is set by a40 v1c t comp delay = (4) where c comp is the capacitor on the comp pin. for a 0.22 f comp capacitor, t delay is 5 ms. after this initial delay, the duty cycle is very low and then ramps up to its final value with the same ramp rate given for t delay . for example, if v in is 16 v and the battery is 10 v when charging is started, the duty cycle is approximately 65%, corresponding to a vcomp of ~2 v. the time for the duty cycle to ramp from 0% at v comp = 1 v to 65% at v comp = 2 v is approximately 5 ms. because the charge current is equal to zero at first, drvl does not turn on. however, if the bst capacitor is discharged, drvl is forced on for a minimum on time of 200 ns each clock period until the bst capacitor is charged to greater than 4 v. typically the bst capacitor is charged in five to ten clock cycles. loop feed forward as described above, the response time at comp is slowed by the large compensation capacitor. to speed up the response, two comparators can quickly feed forward around the normal control loop and pull the comp node down to limit any overshoot in either short-circuit or overvoltage conditions. the overvoltage comparator has a trip point set to 20% higher than the final battery voltage. the overcurrent comparator threshold is set to 180 mv across the cs pins, which is 15% above the maximum programmable threshold. when these comparators are tripped, a normal soft start sequence is initiated. the overvoltage comparator is valuable when the battery is removed during charging. in this case, the current in the inductor causes the output voltage to spike up, and the comparator limits the maximum voltage. neither of these comparators affects the loop under normal charging conditions.
adp3806 rev. c | page 14 of 16 application information design procedure refer to figure 18, the typical application circuit, for the following description. the design follows that of a buck converter. with li-ion cells, it is important to have a regulator with accurate output voltage control. battery voltage settings the adp3806 has three options for voltage selection: ? 12.525 v/16.7 v as selectable fixed voltages ? 12.6 v/16.8 v as selectable fixed voltages ? adjustable when using the fixed versions, r11 should be a short or 0 wire jumper and r12 should be an open circuit. when using the adjustable version, the following equation gives the ratio of the two resistors: 1 5.2 ? ? ? ? ? ? ? = (5) often 0.1% resistors are required to maintain the overall accuracy budget in the design. inductor selection usually the inductor is chosen based on the assumption that the inductor ripple current is 15% of the maximum output dc current at maximum input voltage. as long as the inductor has a value close to this, the system should work fine. the final choice affects the trade-offs between cost, size, and efficiency. for example, if the inductance is lower, the size is smaller but ripple current is higher. this situation, if taken too far, leads to higher ac losses in the core and the windings. conversely, a higher inductance results in lower ripple current and smaller output filter capacitors, but the transient response isslower. with these considerations, the required inductance can be found from s min bat max,in td i vv l1 ? = (6) where the maximum input voltage v in, max is used with the minimum duty ratio d min . the duty ratio is defined as the ratio of the output voltage to the input voltage, v bat /v in . the ripple current is found from maxbat ii , 3.0 = (7) where the maximum peak-to-peak ripple is 30%, that is 0.3, and maximum battery current, i bat, max , is used. for example, with v in, max = 19 v, v bat = 12.6 v, i bat, max = 3a, and t s = 4 s, the value of l1 is calculated as 18.9 h. choosing the closest standard value gives l1 = 22 h. output capacitor selection an output capacitor is needed in the charger circuit to absorb the switching frequency ripple current and smooth the output voltage. the rms value of the output ripple current is given by ( ? = 1 12 , ) (8) the maximum value occurs when the duty cycle is 0.5. thus l1f v i maxin maxrms = , _ 072.0 (9) for an input voltage of 19 v and a 22 h inductance, the maximum rms current is 0.26 a. a typical 10 f or 22 f ceramic capacitor is a good choice to absorb this current. input capacitor ripple as is the case with a normal buck converter, the pulse current at the input has a high rms component. therefore, since the input capacitor has to absorb this current ripple, it must have an appropriate rms current rating. the maximum input rms current is given by () ? = 1 (10) where: is the estimated converter efficiency (approximately 90%, 0.9). p bat is the maximum battery power consumed. this is a worst-case calculation and, depending on total charge time, the calculated number could be relaxed. consult the capacitor manufacturer for further technical information. decoupling the vcc pin it is a good idea to use an rc filter (r13 and c14) from the input voltage to the ic to filter out switching noise and to supply bypass to the chip. during layout, this capacitor should be placed as close to the ic as possible. values between 0.1 f and 2.2 f are recommended.
adp3806 rev. c | page 15 of 16 current-sense filtering during normal circuit operation, the current-sense signals can have high frequency transients that need filtering to ensure proper operation. in the case of the cs+ and cs? inputs, the resistors (r3 and r4) are set to 249 and the filter capacitor (c13) value is 22 nf. for the system current sense circuits, common-mode filtering from sys+ and sys? to ground is needed. 470 nf ceramic capacitors (c1, c2) with 2.2 resistors (r1, r2) usually suffice. these time constants can be adjusted in the laboratory if required but represent a good starting point. mosfet selection one of the features of the adp3806 is that it allows use of a high-side nmos switch instead of a more costly pmos device. the converter also uses synchronous rectification for optimal efficiency. in order to use a high-side nmos, an internal bootstrap regulator automatically generates a 7 v supply across c9. maximum output current determines the r ds(on) requirement for the two power mosfets. when the adp3806 is operating in continuous mode, the simplifying assumption can be made that one of the two mosfets is always conducting the load current. the power dissipation for each mosfet is given by: upper mos p diss = r ds ( on ) ( i bat d ) 2 + v in i bat d t sw f (11) lower mos p diss = r ds ( on ) ( i bat d ) 2 + v in ( i bat i ? d ) 2 t sw f (12) where f is the switching frequency and t sw is the switch transition time, usually 10 ns. the first term accounts for conduction losses and the second term estimates switching losses. using these equations and the manufacturers data sheets, the proper device can be selected. a schottky diode (d1) in parallel with q2 conducts only during dead time between the two power mosfets. the purpose of the d1 is to prevent the body diode of the lower n-channel mosfet from turning on, which could cost as much as 1% in efficiency. one option is to use a combined mosfet with the schottky diode in a single package; these integrated packages often work better in practice. examples are the irf7807d2 and the si4832.
adp3806 rev. c | page 16 of 16 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 21. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model temperature range package description package option adp3806jru-reel 0?c to 100?c adjustable 24-lead tssop adp3806jru-reel7 0?c to 100?c adjustable 24-lead tssop adp3806jruz-reel 1 0?c to 100?c adjustable 24-lead tssop adp3806jruz-reel7 1 0?c to 100?c adjustable 24-lead tssop adp3806jru-12.5-rl 0?c to 100?c 12.525 v/16.7 v 24-lead tssop adp3806jru-12.5-r7 0?c to 100?c 12.525 v/16.7 v 24-lead tssop adp3806jruz-12.5rl 1 0?c to 100?c 12.525 v/16.7 v 24-lead tssop adp3806jruz-12.5-r7 1 0?c to 100?c 12.525 v/16.7 v 24-lead tssop adp3806jru-12.6-rl 0?c to 100?c 12.600 v/16.8 v 24-lead tssop adp3806jru-12.6-r7 0?c to 100?c 12.600 v/16.8 v 24-lead tssop adp3806jruz-12.6-rl 1 0?c to 100?c 12.600 v/16.8 v 24-lead tssop adp3806jruz-12.6-r7 1 0?c to 100?c 12.600 v/16.8 v 24-lead tssop 1 z = pb-free. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. c02611-0-1 1 /06(c)

▲Up To Search▲

Price & Availability of ADP3806JRUZ-125RL

	To Download ADP3806JRUZ-125RL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .